In semiconductor industries, the manufacture of semiconductor devices primarily divides into three stages: wafer fabrication, chip formation, and chip assembly. During wafer fabrication and chip formation processes, a dielectric layer is directly formed on a wafer for die attachment or for wafer-level packaging where the dielectric layer can be B-stage films, solid films or epoxy liquid pastes. However, solid films are more expensive. Therefore, it is more common to dispose liquid pastes on a wafer such as stencil printing on the back surface of a wafer, but the wafer is easily contaminated.
FIG. 1 is the block diagram of a conventional process flow for manufacturing dies with a dielectric layer. Step 1 is to provide a wafer. Step 2 is to attach a protecting tape to the active surface of the wafer to avoid contamination of liquid dielectric materials on the active surface in sequential steps. Step 3 is to turn the wafer upside down with the back surface facing upward. Step 4 is to form a dielectric layer on the back surface of the wafer by stencil printing or any known liquid disposition methods where the cover area of the dielectric layer should be smaller than the one of the back surface of the wafer to avoid liquid bleeding to the sides of the wafer or even to the protecting tape. Step 5 is to thermally cure the dielectric layer on the wafer to reach a certain degree of dryness and curing to avoid serious bleeding in Step 6. In step 5, since the dielectric layer is thermally cured, dimension shrinkage due to curing is unavoidable. Moreover, the wafer is also under heating at the same time, and there is a thermal mismatching issue due to different thermal expansion coefficients and dimensions between the wafer and the dielectric layer. Then, step 6 is to turn the back surface of the wafer downward to attach to a dicing tape so that the dielectric layer is attached to the dicing tape by the adhesion of the dicing tape. Afterward, step 7 is to remove the protecting tape to expose the active surface of the wafer. Then, step 8 is to dice the wafer into a plurality of individual dies. Finally, step 9 is to pick up the dies from the dicing tape. Therefore, the wafer with the dielectric layer will experience multiple heating steps leading to serious wafer warpage issues due to mismatching of thermal expansion coefficients and dimensions, more the worse, the curing shrinkage of dielectric layer causing wafer handling difficulties in the following processes. Furthermore, since the wafer has to go through multiple turning steps, the risk of lower yields and higher cost is relatively increased. Once the back surface of the wafer is not turned upside down in step 6 and the protecting tape is not removed to expose the active surface in step 7, singulation in step 8 has to be done from the back surface of a wafer where scribe line alignment for wafer dicing processes becomes difficult.